High Performance Ultra Low-k (k=2.0/keff=2.4)/Cu Dual-Damascene Interconnect Technology with Self-Formed MnSixOy Barrier Layer for 32 nm-node

• Published in: Proceedings of the IEEE International Interconnect Technology Conference pp. 216 - 218
• Main Authors: Usui, T., Tsumura, K., Nasu, H., Hayashi, Y., Minamihaba, G., Toyoda, H., Sawada, H., Ito, S., Miyajima, H., Watanabe, K., Shimada, M., Kojima, A., Uozumi, Y., Shibata, H.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2006
• Subjects: Atherosclerosis; Capacitance; Copper; Dielectric materials; Electromigration; Indium tin oxide; Metallization; Protection; Research and development; Toy manufacturing industry
• ISBN: 1424401046; 9781424401048
• ISSN: 2380-632X
• DOI: 10.1109/IITC.2006.1648692

In order to realize the effective dielectric constant (k eff)=2.4 for 32 nm-node copper (Cu) dual-damascene (DD) interconnects, a spin-on-dielectric (SOD) SiOC (k=2.0) as the inter-level dielectric and plasma-induced damage restoration treatment were successfully demonstrated. It was obtained that good via resistance and stress-induced voiding (SiV) reliability. In addition, CoW-cap and thin SiC (k=3.5) and dual hard mask process using a metal layer was proposed to reduce the capacitance of dielectric diffusion barrier and protection layers in hybrid (PAr/SiOC) inter-layer dielectric (ILD) structure. As for the metallization, a self-formed MnSi x O y barrier technology was applied in hybrid ILD structure. Drastic reduction of via resistance and excellent electromigration and SiV performance were obtained for the first time in hybrid ILD structure