Pipeline circuit synthesis from Python code - Trost, Andrej; Zemva, Andrej (2017 6th Mediterranean Conference on Embedded Computing (MECO), 2017)
This paper presents methodology and tools for generating pipeline digital circuits from an algorithm specification in Python programming language. The Python language provides a feature rich environment for the algorithm design. Conversion of the algorithm to a register-level code, such as Verilog, requires substantial hardware design and skills. We present a tool for automatic pipeline circuit synthesis from a function in pure Python code and example case.