Pipeline circuit synthesis from Python code

This paper presents methodology and tools for generating pipeline digital circuits from an algorithm specification in Python programming language. The Python language provides a feature rich environment for the algorithm design. Conversion of the algorithm to a register-level code, such as Verilog,...

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Bibliographic Details
Published in2017 6th Mediterranean Conference on Embedded Computing (MECO) pp. 1 - 4
Main Authors Trost, Andrej, Zemva, Andrej
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2017
Subjects
Algorithm design and analysis
Field programmable gate arrays
Hardware
high level synthesis
pipeline circuit
Pipelines
Python
Signal processing
Signal processing algorithms
Verilog
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DOI10.1109/MECO.2017.7977227

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Summary:This paper presents methodology and tools for generating pipeline digital circuits from an algorithm specification in Python programming language. The Python language provides a feature rich environment for the algorithm design. Conversion of the algorithm to a register-level code, such as Verilog, requires substantial hardware design and skills. We present a tool for automatic pipeline circuit synthesis from a function in pure Python code and example case.
DOI:10.1109/MECO.2017.7977227