Design and implementation of a Test Coverage Algorithm for verification and validation of a processor IP core

• Published in: 2016 2nd International Conference on Applied and Theoretical Computing and Communication Technology (iCATccT) pp. 652 - 656
• Main Authors: Prasanna, Kumar N., Yellampalli, Siva, Chetwani, Rajiv R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2016
• Subjects: EDA Tools; Field programmable gate arrays; FPGA; Instruction sets; IP core; IP networks; Radiation hardening (electronics); Registers; Software algorithms; Verification and Validation; VHDL
• DOI: 10.1109/ICATCCT.2016.7912081

This project aims at verification and validation of IP core using software to automatically generate the test suite to cover all possible test cases of a processor IP core. A case study is being taken with an open source processor IP core CPU86 implemented in Very high speed integrated circuit Hardware Description Language (VHDL). The in-house developed Test Coverage Algorithm is used to generate the test cases for CPU86 processor IP core. The test case in the form of the code snippet is converted to processor readable code using certified assembler and is subjected to the verification and validation through simulation by EDA tools. This project directly helps in overcoming obsolescence of radiation hardened processor by using the validated processor IP core fused on FPGA.