Efficient PC-FPGA Communication over Gigabit Ethernet

• Published in: 2010 IEEE 10th International Conference on Computer and Information Technology pp. 1727 - 1734
• Main Authors: Alachiotis, N, Berger, S A, Stamatakis, A
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2010
• Subjects: Clocks; Ethernet networks; Field programmable gate arrays; FPGA; Gigabit Ethernet; Hardware; IP networks; PC-FPGA communication; Protocols; Table lookup; UDP/IP
• ISBN: 1424475473; 9781424475476
• DOI: 10.1109/CIT.2010.302

As FPGAs become larger and more powerful, they are increasingly used as accelerator devices for compute-intensive functions. Input/Output (I/O) speeds can become a bottleneck and directly affect the performance of a reconfigurable accelerator since the chip will idle when there are no data available. While PCI Express represents the currently fastest and most expensive solution to connect a FPGA to a general purpose CPU, there exist several applications with I/O requirements for which Gigabit Ethernet is sufficient. To this end, we present the design of an efficient UDP/IP core for PC-FPGA communication that has been designed to occupy a minimum amount of hardware resources on the FPGA. An observation regarding the internet checksum algorithm, allows us to reduce the hardware requirements for computing the checksum. Furthermore, this property also allows for initiating packet transmission immediately, i.e., the UDP/IP core can start a transmission without the requirement of receiving, storing, and processing user data beforehand. The UDP/IP core is available as open-source code. A comparison with related work on UDP/IP core implementations shows that our implementation is significantly more efficient in terms of resource utilization and performance. The experimental results were obtained on a real-world system and we also make available the PC software test application that is used for performance assessment to allow for reproduction of our results.