A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations

• Published in: 2011 International Conference on Reconfigurable Computing and FPGAs pp. 217 - 222
• Main Authors: He, Wei, de la Torre, Eduardo, Riesgo, Teresa
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2011
• Subjects: AES-128; Delay; DPL (Dual-rail Precharge Logic); Dual-Core; EPE (Early Propagation Effect); Field programmable gate arrays; Logic gates; LUT; Routing; SCA (side channel attack); Switches; Synchronization; Table lookup
• ISBN: 9781457717345; 1457717344
• ISSN: 2325-6532
• DOI: 10.1109/ReConFig.2011.3

In this paper, a new countermeasure against power and electromagnetic (EM) Side Channel Attacks (SCA) on FPGA implemented cryptographic algorithms is proposed. This structure mainly focuses on a critical vulnerability, Early Evaluation, also known as Early Propagation Effect (EPE), which exists in most conventional SCA-hardened DPL (Dual-rail with Precharge Logic) solutions. The main merit of this proposal is that the EPE can be effectively prevented by using a synchronized non regular precharge network, which maintains identical routing between the original and mirror parts, where costs and design complexity compared with previous EPE-resistant countermeasures are reduced, while security level is not sacrificed. Another advantage for our Precharge Absorbed(PA) - DPL method is that its Dual-Core style (independent architecture for true and false parts) could be generated using partial reconfiguration. This helps to get a dynamic security protection with better energy planning. That means system only keeps the true part which fulfills the normal en/decryption task in low security level, and reconfigures the false parts once high security level is required. A relatively limited clock speed is a compromise, since signal propagation is restricted to a portion of the clock period. In this paper, we explain the principles of PA-DPL and provide the guidelines to design this structure. We experimentally validate our methods in a minimized AES co-processor on Xilinx Virtex-5 board using electromagnetic (EM) attacks.