3.2-Gb/s 1024-b rate-1/2 LDPC decoder chip using a flooding-type update-schedule algorithm - Onizawa, N.; Ikeda, T.; Hanyu, T.; Gaudet, V.C. (2007 50th Midwest Symposium on Circuits and Systems, 2007)
Keywords: Bit error rate; Clocks; CMOS technology; Computer architecture; Frequency; Integrated circuit interconnections; Iterative decoding; Parity check codes; Throughput; Wiring