Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained

• Published in: 2008 IEEE International Test Conference pp. 1 - 10
• Main Authors: Bastani, P., Callegari, N., Wang, L.-C., Abadir, M.S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2008
• Subjects: Application specific integrated circuits; Delay; Encoding; Engines; Kernel; Predictive models; Silicon; Support vector machine classification; Support vector machines; Timing
• ISBN: 9781424424023; 142442402X
• ISSN: 1089-3539
• DOI: 10.1109/TEST.2008.4700588

For sub-65 nm design, there can be many timing effects not explicitly and/or accurately modeled and simulated. For design-silicon timing convergence, this paper describes a novel path-based diagnosis approach that analyzes and ranks potential design related issues causing the unexpected timing effects. We explain in detail how a path can be encoded with a set of diverse "features" based on one's knowledge of the potential issues. We explain how these features can be interpreted differently in a data learning algorithm based on adjusting a so-called kernel function. Then, we explain how kernel-based data learning can be used to rank the importance of features such that a feature contributing the most to design-silicon timing mismatch is ranked the highest. We conclude the paper by showing an application result on an industrial ASIC design.