A 65nm 1Gb 2b/Cell NOR Flash with 2.25MB/s Program Throughput and 400MB/s DDR interface - Villa, Corrado; Vimercati, Daniele; Schippers, Stefan; Polizzi, Salvatore; Scavuzzo, Andrea; Perroni, Maurizio; Gaibotti, Maurizio; Sali, Mauro Luigi (2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007)
A 1.8V 1 Gb 2b/cell NOR flash memory is based on a time-domain voltage-ramp reading concept and designed in a 65nm technology. The program method, architecture and algorithm to reach 2.25MB/S programming throughput are presented. The read concept allows 70ns random access time and a 400MB/S sustained read throughput via a DDR interface