Implementation of effective matrix multiplication on FPGA

• Published in: 2011 4th IEEE International Conference on Broadband Network and Multimedia Technology pp. 656 - 658
• Main Authors: Xiaoxiao Jiang, Jun Tao
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2011
• Subjects: Arrays; Field programmable gate arrays; FPGA; Hardware; Hardware Resource; Logic gates; Matrix Multiplication; Radiation detectors; Random access memory; Table lookup
• ISBN: 9781612841588; 1612841589
• DOI: 10.1109/ICBNMT.2011.6156017

Matrix Multiplication is a basic operation that can be used in many applications of DSP. For raw matrix data cannot feed into Simulink Xilinx block directly, thus a new module needs to be designed to complete the matrix multiplication. The original method is straightforward, while consuming considerable hardware resources. In order to save the consumption, we propose a new method to design the matrix multiplication module on Simulink Xilinx platform, which is also implemented on Spartan 3E FPGA (Field Programmable Gate Array). The main idea of the proposal is to reuse the resource and input the data in serial. In this way, the hardware cost can be dramatically decreased; meanwhile decreased but more time for the computation will be needed.