Implementation of Static and Semi-Static Versions of a 24+8×8 Quad-Rail NULL Convention Multiply and Accumulate Unit - Mallepalli, S.R.; Kakarla, S.; Burugapalli, S.; Beerla, S.; Kotla, S.; Sunkara, P.; Al-Assadi, W.K.; Smith, S.C. (2007 IEEE Region 5 Technical Conference, 2007)
Keywords: Algorithm design and analysis; Boolean functions; Clocks; CMOS logic circuits; CMOS process; Delay; Logic circuits; Logic design; Rails; Wires