A high-data-rate low-power BPSK demodulator and clock recovery circuit for implantable biomedical devices

• Published in: 2009 4th International IEEE/EMBS Conference on Neural Engineering pp. 407 - 410
• Main Authors: Asgarian, F., Sodagar, A.M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2009
• Subjects: Binary phase shift keying; binary phase shift keying (BPSK); biomedical implants; Circuits; Clocks; CMOS technology; Data communication; Demodulation; demodulator; Energy consumption; Frequency; high data rate; Implantable biomedical devices; Implants; indutive link; low power; noncoherent; telemetry
• ISBN: 1424420725; 9781424420728
• ISSN: 1948-3546
• DOI: 10.1109/NER.2009.5109319

A novel noncoherent BPSK demodulator is presented for inductively powered biomedical implants. Data demodulation is based on the detection of the rising or falling edge of the digitized received carrier. Ultra low power consumption and high data transmission rate, without increasing the carrier frequency, are accomplished by the outstanding data-rate-to-carrier-frequency ratio of 100%. Thus, the proposed demodulator is especially appropriate for biomedical applications such as cochlear implants and visual prostheses that require high speed data transfer. The circuit is designed in 0.18-mum standard CMOS technology. At a data transmission rate of 20 Mbps, power consumption of the circuit is as low as 310 muW@1.8 V.