Design of high frequency phase locked loop

A digital phase-locked loop (DPLL) is designed using 0.18 mm CMOS process and a 3.3 V power supply. It operates in the frequency range 200 MHz-1 GHz. The DPLL operation includes two stages: (i) a novel coarse-tuning stage based on a flash algorithm, and (ii) a fine-tuning stage similar to convention...

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Bibliographic Details
Published in2010 IEEE International Conference on Communication Control and Computing Technologies pp. 586 - 591
Main Authors Bondare, Raman, Dethe, C G, Bhoyar, D B, Mushrif, M M
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2010
Subjects
Arrays
Decoding
LPF
MCP
PFD
Phase frequency detector
Phase locked loops
Time frequency analysis
VCO
Voltage control
Voltage-controlled oscillators
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ISBN9781424477692
1424477697
DOI10.1109/ICCCCT.2010.5670772

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Summary:A digital phase-locked loop (DPLL) is designed using 0.18 mm CMOS process and a 3.3 V power supply. It operates in the frequency range 200 MHz-1 GHz. The DPLL operation includes two stages: (i) a novel coarse-tuning stage based on a flash algorithm, and (ii) a fine-tuning stage similar to conventional DPLLs. The flash portion of the DPLL is made up of frequency comparators, an encoder and a decoder which drives a multiple charge pump (CP)/low pass filter (LPF) combination. Design considerations of the flash DPLL circuit components as well as implementation using Tanner design tools are presented. Spectra simulations were also performed and demonstrated a significant improvement in the lock time of the flash DPLL as compared to the conventional DPLL.
ISBN:9781424477692
1424477697
DOI:10.1109/ICCCCT.2010.5670772