A Framework on Mitigating Single Event Upset using Delay-Insensitive Asynchronous Circuits

• Published in: 2007 IEEE Region 5 Technical Conference pp. 354 - 357
• Main Author: Jia Di
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2007
• Subjects: Aerospace electronics; Asynchronous circuits; Computer errors; Delay; Error correction; Logic circuits; Logic design; Redundancy; Single event upset; Voting
• ISBN: 142441279X; 9781424412792
• DOI: 10.1109/TPSD.2007.4380334

This framework is a circuit design technique for single event upset (SEU) immunity using delay-insensitive asynchronous logic. SEU can cause a transient fault which, if memorized, will become a soft error. These soft errors are difficult to detect and can lead the circuit to fail. Traditional logical SEU hardening techniques such as error detection and correction (EDAC) and triple modular redundancy (TMR) have their vulnerable points so that they are flawed. This vulnerability can be covered and the overhead can be significantly reduced if dual-rail delay-insensitive logic is used to design the circuits incorporating double modular redundancy (DMR) instead of TMR. With the proposed architecture, this DMR scheme achieves SEU immunity with lower area and power overheads.