Low power DCT architecture for image compression

• Published in: 2013 International Conference on Advanced Computing and Communication Systems pp. 1 - 6
• Main Authors: Vaithiyanathan, D., Seshasayanan, R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2013
• Subjects: Approximation methods; Complexity theory; Computer architecture; DCT approximation; Discrete cosine transforms; Image coding; image compression; low complexity; Multiplication free transform; PSNR; VLSI architecture
• DOI: 10.1109/ICACCS.2013.6938745

In this paper, we have proposed an efficient approximation for the 8-point discrete cosine transform (DCT). The proposed 8×8 transformation matrix contains only zeros and ones which requires only adders, thus avoiding the need for multiplication and bit shift operations. The new class transform requires only 16 additions, which highly reduces the computation complexity with negligible degradation in peak signal to noise ratio (PSNR). We evaluate the performance of the proposed designs in terms of area, speed and power consumption in TSMC 180nm complementary metal-oxide-semiconductor (CMOS) technology. The analysis obtained from the implementation shows that the proposed algorithm is superior to the existing approximation techniques with 25.39% reduction in power and 15.43% area optimization.