G-MAC: an application-specific MAC/co-processor synthesizer

• Published in: 2003 Design, Automation and Test in Europe Conference and Exhibition pp. 1134 - 1135
• Main Authors: Chang, A.C.-Y., Wu-An Kuo, Wu, A.C.-H., Ting Ting Hwang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2003
• Subjects: Coprocessors; Costs; Design engineering; Partitioning algorithms; Pipelines; Process design; Resource management; Sorting; Synthesizers
• ISBN: 0769518702; 9780769518701
• ISSN: 1530-1591
• DOI: 10.1109/DATE.2003.1253769

A modern special-purpose processor (e.g., for image and graphical applications) usually contains a set of instructions supporting complex multiply-operations. These instructions perform a variety of multiply-operations with various data bit-widths and concurrent-execution requirements. For instance, such an instruction set may include instructions to perform signed/unsigned 32/spl times/32, signed/unsigned dual 16/spl times/16, signed/unsigned 8/spl times/8 MAC, and etc. Typically, a co-processor or a complex MAC (Multiplier-ACcumulator) unit is required to execute those instructions. Developing such a complex MAC/co-processor involves a series of design tasks including micro-architecture design, component allocation/binding, interconnect binding, pipeline insertion and control generation. This design process is non-trivial, time-consuming and error-prone, which is usually performed by experienced design engineers. In this paper, we present a synthesis method for application-specific MAC/coprocessor generation. The MAC/co-processor synthesis problem is defined as: Given a set of instructions and the number of execution cycles for each instruction, generate a MAC/co-processor design (including a data-path and a control unit) such that the total area-cost is minimized subject to the given execution-cycle constraints. The MAC/co-processor generation consists of the following two steps. In the first step, we determine a set of minimum-cost components required to realize the given instruction set. In the second step, we perform micro-architectural-level synthesis tasks, including component mapping, interconnect synthesis, pipeline insertion, and control synthesis to generate the MAC/co- processor design.