Design and implementation of a low power spike detection processor for 128-channel spike sorting microsystem

It is impractical to apply a general spike sorting algorithm for every subject because of the individual characteristics of brain signal. Furthermore, extracting more neural activities for higher accuracy of spike sorting requires more input electrodes as well as large power consumption and chip are...

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Bibliographic Details
Published inProceedings of the ... IEEE International Conference on Acoustics, Speech and Signal Processing (1998) pp. 3889 - 3892
Main Authors Tsung-Chuan Ma, Tung-Chien Chen, Liang-Gee Chen
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2014
Subjects
Density measurement
Detection algorithms
Neural Signal Processing
Neurons
Power demand
Power system measurements
Random access memory
Sorting
Spike Detection
Spike Sorting
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ISSN1520-6149
DOI10.1109/ICASSP.2014.6854330

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Summary:It is impractical to apply a general spike sorting algorithm for every subject because of the individual characteristics of brain signal. Furthermore, extracting more neural activities for higher accuracy of spike sorting requires more input electrodes as well as large power consumption and chip area. Therefore, several practical constraints are considered in this work when implementing a programmable spike sorting hardware with large number of input channels. In this paper, we provide a 128-channel spike detection processor for spike sorting microsystem without compromise of the power efficiency. This chip consumes only 87.02uW and 9.7uW/mm 2 of power density, fabricated with 90nm low-leakage CMOS process.
ISSN:1520-6149
DOI:10.1109/ICASSP.2014.6854330