FPGA implementation of high speed Vedic multiplier using CSLA for parallel FIR architecture

• Published in: 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) pp. 1 - 5
• Main Authors: Naaz, S. Amina, Pradeep, M. N., Bhairannawar, Satish, Halvi, Srinivas
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.03.2014
• Subjects: Adders; Arrays; Delays; Digital signal processing; FFA (FAST FIR ALGORITHM); Finite impulse response filters; FIR (FINITE IMPULSE RESPONSE); Parallel FIR Architecture; Signal processing algorithms; Urdhya Tiryakbhyam; Vedic Mathematics
• DOI: 10.1109/ICDCSyst.2014.6926136

In today's world lots of research work is going in the field of communication and signal processing applications. Every application demands for a higher throughput arithmetic operation. One of the key arithmetic operations is multiplication which takes maximum execution time. The development of efficient multiplier is a subject of interest over decades. So there is a need for an efficient multiplier which obtains higher performance for real time signal processing application. This paper presents the modular design of Vedic multiplier using carry select adder. The delay of proposed multiplier is reduced due to high speed carry select adder. The proposed multiplier is applied to parallel FIR filter. It can be observed that the combinational delay reduced for the proposed multiplier compared to existing architecture.