Partially-parallel irregular LDPC decoder based on improved message passing schedule

In this paper, we propose a new efficient message-passing schedule for irregular LPDC code. Our approach is based on the schedule designed for regular LDPC code. We have modified the original schedule for regular LDPC code and improved it particularly for the irregular LDPC coder realization. The ex...

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Bibliographic Details
Published in2007 50th Midwest Symposium on Circuits and Systems pp. 1473 - 1476
Main Authors Xing Li, Shimizu, K., Zhen Qiu, Ikenaga, T., Goto, S.
Format Conference Proceeding
LanguageEnglish
Japanese
Published IEEE 01.08.2007
Subjects
Bit error rate
CMOS technology
Decoding
Error correction codes
Hardware
Message passing
Parity check codes
Processor scheduling
Production systems
Throughput
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ISBN1424411750
9781424411757
ISSN1548-3746
DOI10.1109/MWSCAS.2007.4488821

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Summary:In this paper, we propose a new efficient message-passing schedule for irregular LPDC code. Our approach is based on the schedule designed for regular LDPC code. We have modified the original schedule for regular LDPC code and improved it particularly for the irregular LDPC coder realization. The experimental results show that our method could achieve better performance than conventional one, and improve the converging rate as well.
ISBN:1424411750
9781424411757
ISSN:1548-3746
DOI:10.1109/MWSCAS.2007.4488821