An FPGA based Real time Implementation of Nosé hoover Chaotic System using different numerical Techniques

In this paper, we have implemented the Nosé-Hoover chaotic generator by numerically coding the differential equations in Python and modeling them in Xilinx Kintex 7 FPGA development environment using Euler's, Heun's, and Runge Kutta's 4th order-based algorithms in Verilog HDL. The pe...

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Bibliographic Details
Published inInternational Conference on Advanced Computing and Communication Systems (Online) Vol. 1; pp. 108 - 113
Main Authors Garg, Ayush, Yadav, Bhola, Sahu, Kaustuv, Suneja, Kriti
Format Conference Proceeding
LanguageEnglish
Published IEEE 19.03.2021
Subjects
chaos
Chaotic communication
Computational modeling
Data models
Euler's method
FPGA
Generators
Heun's method Runge-Kutta's 4th order method
LUTs
Nosé-hover
Numerical models
Software algorithms
Throughput
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ISBN9781665405201
1665405201
ISSN2575-7288
DOI10.1109/ICACCS51430.2021.9441923

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Summary:In this paper, we have implemented the Nosé-Hoover chaotic generator by numerically coding the differential equations in Python and modeling them in Xilinx Kintex 7 FPGA development environment using Euler's, Heun's, and Runge Kutta's 4th order-based algorithms in Verilog HDL. The performance of these algorithms has been analyzed by comparing Slice LUTs used, delay, DSPs, etc. The accuracy of the HDL implementation of each algorithm has been analyzed by calculating Root Mean Square Error(RMSE). In addition, the computation time of PC-based and FPGA-based implementation also have been compared for each algorithm.
ISBN:9781665405201
1665405201
ISSN:2575-7288
DOI:10.1109/ICACCS51430.2021.9441923