A Real Time FPGA Implementation and Analysis of a Novel Chaotic System

In this paper, we have designed and implemented a Novel chaos generator having cubic non-linearities for supporting higher levels of encryption. We have modelled our generator using Verilog Hardware Description Language on Xilinx Kintex 7 FPGA development environment by utilizing Runge Kutta's...

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Published in2022 International Conference for Advancement in Technology (ICONAT) pp. 1 - 4
Main Authors Yadav, Bhola, Garg, Ayush, Sahu, Kaustuv, Suneja, Kriti
Format Conference Proceeding
LanguageEnglish
Published IEEE 21.01.2022
Subjects
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DOI10.1109/ICONAT53423.2022.9725976

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Abstract In this paper, we have designed and implemented a Novel chaos generator having cubic non-linearities for supporting higher levels of encryption. We have modelled our generator using Verilog Hardware Description Language on Xilinx Kintex 7 FPGA development environment by utilizing Runge Kutta's 4th order-based algorithms for mathematical analysis. The mathematical analysis of the proposed novel chaos generator has been carried out using python. The proposed system is implemented on the FPGA and is verified using bifurcation diagram and Lyapunov's exponent. Several aspects such as Slice LUTs used, delay, DSPs, etc. have been calculated to analyse the performance of the proposed system.
AbstractList In this paper, we have designed and implemented a Novel chaos generator having cubic non-linearities for supporting higher levels of encryption. We have modelled our generator using Verilog Hardware Description Language on Xilinx Kintex 7 FPGA development environment by utilizing Runge Kutta's 4th order-based algorithms for mathematical analysis. The mathematical analysis of the proposed novel chaos generator has been carried out using python. The proposed system is implemented on the FPGA and is verified using bifurcation diagram and Lyapunov's exponent. Several aspects such as Slice LUTs used, delay, DSPs, etc. have been calculated to analyse the performance of the proposed system.
Author Garg, Ayush
Yadav, Bhola
Suneja, Kriti
Sahu, Kaustuv
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  organization: Delhi Technological University,Dept. of Electronics and Communication Engineering
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Snippet In this paper, we have designed and implemented a Novel chaos generator having cubic non-linearities for supporting higher levels of encryption. We have...
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SubjectTerms Analytical models
Bifurcation
Chaos
Chaos Generator
Encryption
FPGA
Generators
Lyapunov's exponents
Lyapunov's Stability
Mathematical analysis
Real-time systems
RK4
Trajectory
Xilinx Vivado
Title A Real Time FPGA Implementation and Analysis of a Novel Chaotic System
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