Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy

It is generally impossible to store all weights into an MLP accelerator because of limited on-chip SRAM capacity. However, the performance can still be improved if a portion of weights are allocated in faster SRAM. In this paper, we first present an analytical method for performance evaluation under...

Full description

Saved in:
Bibliographic Details
Published inProceedings of Technical Program of International Symposium on VLSI Design, Automation and Test pp. 1 - 4
Main Authors Fan, Kang-Yi, Chen, Jyun-Hua, Liu, Chien-Nan, Huang, Juinn-Dar
Format Conference Proceeding
LanguageEnglish
Published IEEE 18.04.2022
Subjects
deep learning
Heuristic algorithms
ILP
Life estimation
Loading
MLP accelerator
Performance evaluation
performance optimization
Random access memory
Runtime
Very large scale integration
weight allocation
Online AccessGet full text
ISSN2472-9124
DOI10.1109/VLSI-DAT54769.2022.9768095

Cover

More Information
Summary:It is generally impossible to store all weights into an MLP accelerator because of limited on-chip SRAM capacity. However, the performance can still be improved if a portion of weights are allocated in faster SRAM. In this paper, we first present an analytical method for performance evaluation under different weight allocation approaches. We then propose an ILP-based on-chip weight allocation strategy that can maximize the overall performance. Experiment results show that the proposed strategy constantly outperforms several trivial heuristic methods over a large set of various MLP models, MLP accelerator configurations, and on-chip SRAM capacities.
ISSN:2472-9124
DOI:10.1109/VLSI-DAT54769.2022.9768095