Introduction of Noise-Shaping SAR ADCs

• Published in: Proceedings of Technical Program of International Symposium on VLSI Design, Automation and Test p. 1
• Main Author: Shu, Yun-Shiang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 18.04.2022
• Subjects: Analog-digital conversion; Delta-sigma modulation; Design automation; Matched filters; Noise shaping; Quantization (signal); Very large scale integration
• ISSN: 2472-9124
• DOI: 10.1109/VLSI-DAT54769.2022.9768054

SAR ADCs have been getting more and more attention as technology scaling continues. Their mostly digital nature enjoys full benefit of advanced processes and leads to highly power- and area-efficient ADC designs. However, the resolution of SAR ADCs is usually around 10-12 bits limited by the comparator noise and DAC mismatch. By contrast, delta-sigma modulators can achieve highresolution A/D conversion using low-resolution quantizers and DACs; therefore, high comparator noise is acceptable, and DAC mismatch error can be alleviated by dynamic element matching (DEM). Nevertheless, delta-sigma modulators rely on analog filters to suppress the quantization error and do not benefit much from technology scaling. Recently, an emerging ADC architecture, called noiseshaping SAR, takes the advantages of both SAR ADCs and delta-sigma modulators to achieve high power efficiency and high resolution simultaneously. This talk will introduce the fundamental principle of noise-shaping SAR architecture and bring out the recent advances of circuit techniques that enhance the performance of noise-shaping SAR ADCs for different applications.