Design and Analysis of Sobol Sequence Generator using gray code parallelization

This paper discusses the various methods of generating the Sobol sequence, a quasi-random number sequence, and introduces a new architecture for its generation. The proposed algorithm exploits the property of gray code, which minimizes the number of computations in the generation of Sobol sequence r...

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Bibliographic Details
Published in2021 2nd Global Conference for Advancement in Technology (GCAT) pp. 1 - 6
Main Authors Dikshit, Akriti, Prasad, Gayathri, Ponnambalam, Maran
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2021
Subjects
Computer architecture
Field programmable gate arrays
FPGAs
Generators
Hardware
Quasi-random number
Reflective binary codes
Sobol Sequence
Throughput
Virtex-4
Virtex-6
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DOI10.1109/GCAT52182.2021.9587580

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Summary:This paper discusses the various methods of generating the Sobol sequence, a quasi-random number sequence, and introduces a new architecture for its generation. The proposed algorithm exploits the property of gray code, which minimizes the number of computations in the generation of Sobol sequence random numbers using 4X parallelization. This paper also focuses on the comparison of the run time of the proposed method in Python with the three other modifications and the original Sobol sequence method. Further, when compared in Xilinx Virtex-4 and 6 FPGAs, the throughput/area ratio of the proposed method is comparatively higher than the other reported modifications of the Sobol sequence random number generators with a considerable hardware utilization.
DOI:10.1109/GCAT52182.2021.9587580