A64FX: 52 Core Processor Designed for the Supercomputer Fugak
Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. In supercomputing, high-performance computing (HPC) applications require large amounts of parallel processing capability and high memory bandwidth. Recently, a...
Saved in:
| Published in | Proceedings of Technical Program of International Symposium on VLSI Design, Automation and Test p. 1 |
|---|---|
| Main Author | |
| Format | Conference Proceeding |
| Language | English |
| Published |
IEEE
18.04.2022
|
| Subjects | |
| Online Access | Get full text |
| ISSN | 2472-9124 |
| DOI | 10.1109/VLSI-DAT54769.2022.9768080 |
Cover
| Abstract | Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. In supercomputing, high-performance computing (HPC) applications require large amounts of parallel processing capability and high memory bandwidth. Recently, artificial intelligence (AI) applications, which have characteristics similar to HPC applications, have played an important role in supercomputers. The supercomputer Fugaku has a large number of general-purpose processors for high performance, high-density implementation as well as low power consumption to realize a massive parallel system for multiple applications targeting HPC and AI. Furthermore, in terms of availability, reliability in large-scale systems such as Fugaku is important. Fugaku is a supercomputer comprising >7.6 million cores and has remained No.1 in the Top 500 for three consecutive terms because it achieved 442 Petaflops at 29.9 Mega Wat in June 2020. In this session, for large-scale systems, we describe how CPUs in Fugaku solve challenges of high performance, low power consumption, and reliability. |
|---|---|
| AbstractList | Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. In supercomputing, high-performance computing (HPC) applications require large amounts of parallel processing capability and high memory bandwidth. Recently, artificial intelligence (AI) applications, which have characteristics similar to HPC applications, have played an important role in supercomputers. The supercomputer Fugaku has a large number of general-purpose processors for high performance, high-density implementation as well as low power consumption to realize a massive parallel system for multiple applications targeting HPC and AI. Furthermore, in terms of availability, reliability in large-scale systems such as Fugaku is important. Fugaku is a supercomputer comprising >7.6 million cores and has remained No.1 in the Top 500 for three consecutive terms because it achieved 442 Petaflops at 29.9 Mega Wat in June 2020. In this session, for large-scale systems, we describe how CPUs in Fugaku solve challenges of high performance, low power consumption, and reliability. |
| Author | Tabata, Takekazu |
| Author_xml | – sequence: 1 givenname: Takekazu surname: Tabata fullname: Tabata, Takekazu organization: Fujitsu Limited |
| BookMark | eNotj0tLw0AURkdRsNb8AjeD-8S5k3ldwUVIjRYCCg3iruRxU6M2CZNm4b-3YDff4WwOfNfsoh96YuwORAQg8P4936zDVVJoZQ1GUkgZoTVOOHHGArQOjNFKoARzzhZSWRkiSHXFgmn6EkKAARM7tWCPiVHZxwPXkqeDJ_7mh5qmafB8RVO366nh7VEOn8Q380i-HvbjfCDPs3lXft-wy7b8mSg4ccmK7KlIX8L89XmdJnnYKQdhRbpCRQCxkwiijRXEWDUkrJBNq7AFe9wKmrKqldamAaTalWAt1qXGOl6y2_9sR0Tb0Xf70v9uT3_jPyKHSuU |
| ContentType | Conference Proceeding |
| DBID | 6IE 6IL CBEJK RIE RIL |
| DOI | 10.1109/VLSI-DAT54769.2022.9768080 |
| DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Xplore POP ALL IEEE Xplore All Conference Proceedings IEEE Electronic Library (IEL) IEEE Proceedings Order Plans (POP All) 1998-Present |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) - 2025 collection url: https://proxy.k.utb.cz/login?url=https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering |
| EISBN | 9781665409216 1665409215 |
| EISSN | 2472-9124 |
| EndPage | 1 |
| ExternalDocumentID | 9768080 |
| Genre | teaser-abstract |
| GroupedDBID | 6IE 6IF 6IH 6IK 6IL 6IN AAJGR AAWTH ABLEC ADZIZ ALMA_UNASSIGNED_HOLDINGS BEFXN BFFAM BGNUA BKEBE BPEOZ CBEJK CHZPO IEGSK IPLJI OCL RIE RIL RNS |
| ID | FETCH-LOGICAL-i481-be5b94e11382910f34139bde0702df49f17f49b1dabc4556d19ec8a1779ca59c3 |
| IEDL.DBID | RIE |
| IngestDate | Wed Aug 27 02:12:34 EDT 2025 |
| IsPeerReviewed | false |
| IsScholarly | true |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-i481-be5b94e11382910f34139bde0702df49f17f49b1dabc4556d19ec8a1779ca59c3 |
| PageCount | 1 |
| ParticipantIDs | ieee_primary_9768080 |
| PublicationCentury | 2000 |
| PublicationDate | 2022-April-18 |
| PublicationDateYYYYMMDD | 2022-04-18 |
| PublicationDate_xml | – month: 04 year: 2022 text: 2022-April-18 day: 18 |
| PublicationDecade | 2020 |
| PublicationTitle | Proceedings of Technical Program of International Symposium on VLSI Design, Automation and Test |
| PublicationTitleAbbrev | VLSI-DAT |
| PublicationYear | 2022 |
| Publisher | IEEE |
| Publisher_xml | – name: IEEE |
| SSID | ssj0001616384 |
| Score | 2.1815362 |
| Snippet | Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. In supercomputing,... |
| SourceID | ieee |
| SourceType | Publisher |
| StartPage | 1 |
| SubjectTerms | Artificial intelligence Large-scale systems Parallel processing Power demand Reliability engineering Supercomputers Very large scale integration |
| Title | A64FX: 52 Core Processor Designed for the Supercomputer Fugak |
| URI | https://ieeexplore.ieee.org/document/9768080 |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV3LSgMxFA1tV7rx0YpvsnBpps00yUwEF6V1qGJFaJXuSh43IoW2lM7GrzeZjq2KCzchBBJCLuEcknvORejKg0JijTTEaeUIUzEQpQQQ7aEvDTUmXZHyP3gS_Rf2MObjCrreaGEAoEg-gyh0i798Ozd5eCprhvme4VRRNUnFWqu1fU8RgVmw0leUtmTz9XF4T3qdEWeJCJKUOI7KBX5UUimAJNtDg68trPNHplG-0pH5-OXO-N897qPGVrKHnzdgdIAqMDtEu9_cBuvotiNYNr7BPMZdvyouNQLzJe4VaRxgsWew2DNCPMwXsDRlwQec5W9q2kCj7G7U7ZOyegJ5ZyklGriWDGjwGPSUwAW0ktqCv-KxdUw6mvhWU6u0YZwLSyWYVNEkkUZxadpHqDabz-AY4ZZOdRuE5UanrO0KTzBHbdIybaNZTE9QPZzDZLH2x5iUR3D69_AZ2gmxCD8yND1HtdUyhwsP7Ct9WUT0E7_8oQE |
| linkProvider | IEEE |
| linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV1NTwIxFGwQD-rFDzB-24NHC3S33d2aeCDgBhSICavhRrbtqzEkQAh78dfbLiuo8eClaZq0afrSzKR9Mw-hGwsKoVZCESNTQ1jqAUnTAIi00Be5GpMmT_nvD4LOC3sc8VEJ3a61MACQJ59BzXXzv3w9U5l7Kqu7-ZbhbKFtzhjjK7XW5kUlcNyCFc6itCHqr71hl7SbCWdh4EQpnlcrlvhRSyWHkngf9b82scogmdSypaypj1_-jP_d5QGqbkR7-HkNR4eoBNMjtPfNb7CC7psBi0d3mHu4ZVfFhUpgtsDtPJEDNLYcFltOiIfZHBaqKPmA4-wtnVRREj8krQ4p6ieQdxZRIoFLwYA6l0FLCozDKyE12EvuacOEoaFtJdWpVIzzQFMBKkppGAqVcqH8Y1SezqZwgnBDRtKHQHMlI-ab3BXMUB02lK8k8-gpqrhzGM9XDhnj4gjO_h6-RjudpN8b97qDp3O06-Li_mdodIHKy0UGlxbml_Iqj-4nYxykTg |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=Proceedings+of+Technical+Program+of+International+Symposium+on+VLSI+Design%2C+Automation+and+Test&rft.atitle=A64FX%3A+52+Core+Processor+Designed+for+the+Supercomputer+Fugak&rft.au=Tabata%2C+Takekazu&rft.date=2022-04-18&rft.pub=IEEE&rft.eissn=2472-9124&rft.spage=1&rft.epage=1&rft_id=info:doi/10.1109%2FVLSI-DAT54769.2022.9768080&rft.externalDocID=9768080 |