Beyond DVFS: A First Look at Performance under a Hardware-Enforced Power Bound

• Published in: 2012 26th IEEE International Parallel and Distributed Processing Symposium Workshops pp. 947 - 953
• Main Authors: Rountree, B., Ahn, D. H., de Supinski, B. R., Lowenthal, D. K., Schulz, M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2012
• Subjects: Benchmark testing; Clamps; Computer architecture; Power bound; Power demand; Power measurement; Program processors; RAPL; Time measurement
• ISBN: 1467309745; 9781467309745
• DOI: 10.1109/IPDPSW.2012.116

Dynamic Voltage Frequency Scaling (DVFS) has been the tool of choice for balancing power and performance in high-performance computing (HPC). With the introduction of Intel's Sandy Bridge family of processors, researchers now have a far more attractive option: user-specified, dynamic, hardware-enforced processor power bounds. In this paper we provide a first look at this technology in the HPC environment and detail both the opportunities and potential pitfalls of using this technique to control processor power. As part of this evaluation we measure power and performance for single-processor instances of several of the NAS Parallel Benchmarks. Additionally, we focus on the behavior of a single benchmark, MG, under several different power bounds. We quantify the well-known manufacturing variation in processor power efficiency and show that, in the absence of a power bound, this variation has no correlation to performance. We then show that execution under a power bound translates this variation in efficiency into variation in performance.