APA (7th ed.) Citation

Usami, K., Nakata, M., Shirai, T., Takeda, S., Seki, N., Amano, H., & Nakamura, H. (2009, May). Implementation and evaluation of fine-grain run-time power gating for a multiplier. 2009 IEEE International Conference on IC Design and Technology, 7-10. https://doi.org/10.1109/ICICDT.2009.5166253

Chicago Style (17th ed.) Citation

Usami, K., M. Nakata, T. Shirai, S. Takeda, N. Seki, H. Amano, and H. Nakamura. "Implementation and Evaluation of Fine-grain Run-time Power Gating for a Multiplier." 2009 IEEE International Conference on IC Design and Technology May. 2009: 7-10. https://doi.org/10.1109/ICICDT.2009.5166253.

MLA (9th ed.) Citation

Usami, K., et al. "Implementation and Evaluation of Fine-grain Run-time Power Gating for a Multiplier." 2009 IEEE International Conference on IC Design and Technology, May. 2009, pp. 7-10, https://doi.org/10.1109/ICICDT.2009.5166253.