A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs - Fujiwara, Koichi; Abe, Shinya; Kawamura, Kazushi; Yanagisawa, Masao; Togawa, Nozomu (APCCAS : 2014 IEEE Asia Pacific Conference on Circuits and Systems : 17-20 November 2014, 2014)
Keywords: Algorithm design and analysis; Data transfer; Delays; Field programmable gate arrays; Integrated circuit interconnections; Registers; Table lookup