A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs

• Published in: APCCAS : 2014 IEEE Asia Pacific Conference on Circuits and Systems : 17-20 November 2014 pp. 244 - 247
• Main Authors: Fujiwara, Koichi, Abe, Shinya, Kawamura, Kazushi, Yanagisawa, Masao, Togawa, Nozomu
• Format: Conference Proceeding
• Language: English; Japanese
• Published: IEEE 01.11.2014
• Subjects: Algorithm design and analysis; Data transfer; Delays; Field programmable gate arrays; Integrated circuit interconnections; Registers; Table lookup
• DOI: 10.1109/APCCAS.2014.7032765

Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications such as computerized stock tradings and reconfigurable network processings. In HLS for FPGA designs, we need to consider module floorplan and reduce multiplexer's cost concurrently. In this paper, we propose a floorplan-aware HLS algorithm for multiplexer reduction targeting FPGA designs. By utilizing distirbuted-register architectures called HDR, we can easily consider module floorplan in HLS. In order to reduce multiplexer's cost, we propose two novel binding methods called datapath-oriented scheduling/FU binding and datapath-oriented register binding. Experimental results demonstrate that our algorithm can realize FPGA designs which reduces the number of slices by up to 47% and circuit delay by up to 16% compared with the conventional approach.