Improvement of LDO's PSRR deteriorated by reducing power consumption : Implementation and experimental results

• Published in: 2009 IEEE International Conference on IC Design and Technology pp. 11 - 15
• Main Authors: Socheat Heng, Cong-Kha Pham
• Format: Conference Proceeding
• Language: English; Japanese
• Published: IEEE 01.05.2009
• Subjects: Bandwidth; Circuit noise; Circuit testing; Energy consumption; Equations; Error Amplifier; Frequency; Low Dropout Regulator; Low Power; Low Voltage; Noise reduction; Power supplies; Power Supply Rejection Ratio; Regulators; Voltage
• ISBN: 1424429331; 9781424429332
• ISSN: 2381-3555
• DOI: 10.1109/ICICDT.2009.5166254

In this work, a Bulk-Gate Controlled Circuit, for improving power supply rejection ratio (PSRR) of a Low Dropout Voltage Regulator (LDO) which deteriorates due to lowering of power consumption is proposed. A test chip was fabricated using 0.18-mum CMOS process. Experimental results of the test chip demonstrate that the proposed circuit provides a high performance of PSRR which is up to 77 dB at 10 Hz, and 64.3 dB at 1 KHz, while the consumption current of the whole LDO which includes currents of all component circuits such as a reference circuit, an over current protection circuit, etc., is reduced to 8.5 muA without load, and 35 muA with full load. Comparing to the basic type of conventional LDOs, PSRR of the proposed bulk-gate controlled LDO achieves an improvement of 16 dB for 10 Hz and 27.8 dB for 1 KHz .