A parallel hardware architecture for connected component labeling based on fast label merging - Flatt, H.; Blume, S.; Hesselbarth, S.; Schunemann, T.; Pirsch, P. (2008 International Conference on Application-Specific Systems, Architectures and Processors, 2008)
This paper presents a dedicated parallel hardware architecture for fast connected component labeling. Both, label generation and merging of equivalent labels are accelerated. Label generation is performed for four pixels in parallel. A special linked list based approach for fast label merging is proposed. This results in a compact implementation and shorter processing times compared to published implementations. For prototyping and evaluation purposes, the hardware architecture was integrated into an FPGA-based modular coprocessor architecture. A binary D1 test image is labeled in 1.74 ms on a Virtex-II Pro FPGA running at 140 MHz. Moreover, the architecture can be easily integrated into embedded image processing systems.