Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processor

• Published in: 2008 International Conference on Application-Specific Systems, Architectures and Processors pp. 245 - 250
• Main Authors: Garcia, A., Berekovic, M., Aa, T.V.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.07.2008
• Subjects: Arrays; Cryptography; Digital signal processing; Embedded system; Optimization; Table lookup; Titanium
• ISBN: 9781424418978; 1424418976
• ISSN: 1063-6862
• DOI: 10.1109/ASAP.2008.4580186

Coarse-Grained reconfigurable architectures are emerging as potential candidates to meet the high performance, power efficiency and flexibility needed by embedded systems. ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its DRESC compiler offer a very promising platform for designing embedded systems targeted for different application domains. We present a procedure for mapping the widely used AES cryptographic algorithm on ADRES. A detailed explanation is shown for each of the optimizations performed in order to make better use of instruction and loop parallelism. A new intrinsic function set is proposed for speeding up the processing of the AES algorithm. The obtained simulation results are compared with experiments done on the widely known Texas Instruments DSP: TI C64x, which is considered state-of-the-art for embedded systems. Our results show that ADRES outperforms TI C64x DSP, executing the AES algorithm in one fourth of the cycles.