Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and ImplantBench workloads

• Published in: 2010 IEEE International Symposium on Performance Analysis of Systems and Software pp. 33 - 44
• Main Authors: Ganesan, Karthik, Jungho Jo, John, Lizy K
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.03.2010
• Subjects: Application software; Character generation; Cloning; Computational modeling; Computer aided instruction; Computer applications; Computer simulation; Microarchitecture; Parallel processing; Time sharing computer systems
• ISBN: 1424460239; 9781424460236
• DOI: 10.1109/ISPASS.2010.5452076

We generate and provide miniature synthetic benchmark clones for modern workloads to solve two pre-silicon design challenges, namely: 1) huge simulation time (weeks to months) when using complete runs of modern workloads like SPEC CPU2006 having trillions of instructions on pre-silicon design models 2) unavailability of access to their specific target applications for computer architects, as some of them are proprietary in nature and vendors hesitate to share them. We first provide a detailed characterization of the SPEC CPU2006 and the ImplantBench suites based on microarchitecture-independent metrics. Our metrics include the Memory Level Parallelism (MLP) of these workloads to estimate the burstiness of accesses to the main memory. Secondly, our proposed framework, that uses this characterized information (including MLP) to generate synthetic clones is explained and evaluated. We provide the synthetic clones generated for CPU2006 workloads for download and use. The efficacy of the synthetic clones for CPU2006 and ImplantBench is demonstrated by comparing their performance and power characteristics with their original counterparts. We show that the synthetic clones generated using our MLP-aware methodology have an error of only 2.8% in terms of Instruction Per Cycle (IPC) as compared to an error of 15.3% when using the previous MLP-unaware approaches for CPU2006. We also evaluate their effectiveness in assessing the change in performance and power consumption for various microarchitecture design changes. For CPU2006, with synthetics limited to 1 million dynamic instructions, the average correlation coefficient for assessing design changes for IPC is 0.95 (0.98 for power-per-cycle). For ImplantBench, we have an average error of 2.9% in assessing the IPC and the correlation coefficient for assessing design changes is 0.94 (0.97 for power-per-cycle).