A partial redundant fault-secure high-level synthesis algorithm for RDR architectures - Kawamura, Kazushi; Tanaka, Sho; Yanagisawa, Masao; Togawa, Nozomu (2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013)
In this paper, we propose a partial redundant fault-secure high-level synthesis algorithm for RDR architectures, where we duplicate a part of the original CDFG and maximize its reliability under a timing constraint. Firstly, our algorithm allocates some new additional functional units to vacant spaces on RDR islands for recomputation and increases the number of duplicated operation nodes. Secondly, it minimizes the number of inserted comparator nodes through re-scheduling/re-binding the recomputation CDFG's nodes. As a result, we will obtain a scheduled/bound recomputation CDFG and renewed functional unit allocation with high reliability. Experimental results demonstrate that our algorithm improves reliability by up to 52% compared with the conventional approach.