A partial redundant fault-secure high-level synthesis algorithm for RDR architectures

In this paper, we propose a partial redundant fault-secure high-level synthesis algorithm for RDR architectures, where we duplicate a part of the original CDFG and maximize its reliability under a timing constraint. Firstly, our algorithm allocates some new additional functional units to vacant spac...

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Bibliographic Details
Published in2013 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1736 - 1739
Main Authors Kawamura, Kazushi, Tanaka, Sho, Yanagisawa, Masao, Togawa, Nozomu
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2013
Subjects
Circuit faults
Computer architecture
Delays
Multiplexing
Registers
Reliability
Resource management
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ISBN9781467357609
146735760X
ISSN0271-4302
DOI10.1109/ISCAS.2013.6572200

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Summary:In this paper, we propose a partial redundant fault-secure high-level synthesis algorithm for RDR architectures, where we duplicate a part of the original CDFG and maximize its reliability under a timing constraint. Firstly, our algorithm allocates some new additional functional units to vacant spaces on RDR islands for recomputation and increases the number of duplicated operation nodes. Secondly, it minimizes the number of inserted comparator nodes through re-scheduling/re-binding the recomputation CDFG's nodes. As a result, we will obtain a scheduled/bound recomputation CDFG and renewed functional unit allocation with high reliability. Experimental results demonstrate that our algorithm improves reliability by up to 52% compared with the conventional approach.
ISBN:9781467357609
146735760X
ISSN:0271-4302
DOI:10.1109/ISCAS.2013.6572200