SYSCORE: A Coarse Grained Reconfigurable Array Architecture for Low Energy Biosignal Processing

• Published in: 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines pp. 109 - 112
• Main Authors: Patel, K, McGettrick, S, Bleakley, C J
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2011
• Subjects: Arrays; biosignal; coarse grained reconfigurable architecture; Copper; Digital signal processing; Energy consumption; low energy; Random access memory; Registers; systolic
• ISBN: 9781612842776; 1612842771
• DOI: 10.1109/FCCM.2011.38

The promise of 24/7 patient monitoring and online diagnosis using wearable and implantable biomedical devices has engendered significant research interest in the development of low power biosignal processing platforms. A novel Coarse Grained Reconfigurable Array (CGRA) architecture is presented for low power, real time processing of biomedical signals. The proposed architecture differs from previously proposed CGRAs in that it is designed for low power, rather than for high performance. The proposed architecture was implemented in a software modeler and simulator and in Verilog. The architecture was shown to provide average savings in energy consumption of 62% compared to conventional DSP and SIMD processors and average speed ups of 30× and 8×, respectively, for typical biosignal processing algorithms.