Investigating execution-characteristics of feature-detection algorithms

• Published in: 2017 22nd IEEE International Conference on Emerging Technologies and Factory Automation (ETFA) Vol. Part F134116; pp. 1 - 4
• Main Authors: Danielsson, Jakob, Jagemar, Marcus, Behnam, Moris, Sjodin, Mikael
• Format: Conference Proceeding Journal Article
• Language: English
• Published: IEEE 01.01.2017
• Subjects: Detection algorithms; Feature extraction; Hardware; Monitoring; Prediction algorithms; Velocity measurement
• ISSN: 1946-0740; 1946-0759; 1946-0759
• DOI: 10.1109/ETFA.2017.8247758

We discuss how to obtain information of execution characteristics, such as parallelizability and memory utilization, with the final aim to improve the performance and predictability of feature and corner detection algorithms for use in e.g. robotics and autonomous machines. Our aim is to obtain a better understanding of how computer vision algorithms use hardware resources and how to improve the time predictability and execution time of such algorithms when executing on multi-core CPUs. We evaluate a fork-join model applicable to feature detection algorithms and present a method for measuring how well the algorithm performance correlates with hardware resource usage. We have applied our method to the Featured from Accelerated Segment Test (FAST) algorithm. Our characterization of FAST reveals that it is an algorithm with excellent parallelism opportunities, resulting in an almost linear speed-up per core. Our measurements also reveal that the performance of FAST correlates very little with the number of misses in the L1 data cache, L1 instruction cache, data translation lookaside buffer and L2 cache. Thus, the FAST algorithm will not have a negative effect on the execution time when the input data fits in the L2 cache.