APA (7th ed.) Citation

Zhao, Z., Li, J., Chen, G., Jiang, Z., Qiao, R., Xu, P., . . . Lu, H. (2024, May 19). An FPGA-Based High-Throughput Dataflow Accelerator for Lightweight Neural Network. IEEE International Symposium on Circuits and Systems proceedings, 1-5. https://doi.org/10.1109/ISCAS58744.2024.10558315

Chicago Style (17th ed.) Citation

Zhao, Zhiyuan, Jixing Li, Gang Chen, Zhelong Jiang, Ruixiu Qiao, Peng Xu, Yihao Chen, and Huaxiang Lu. "An FPGA-Based High-Throughput Dataflow Accelerator for Lightweight Neural Network." IEEE International Symposium on Circuits and Systems Proceedings 19 May. 2024: 1-5. https://doi.org/10.1109/ISCAS58744.2024.10558315.

MLA (9th ed.) Citation

Zhao, Zhiyuan, et al. "An FPGA-Based High-Throughput Dataflow Accelerator for Lightweight Neural Network." IEEE International Symposium on Circuits and Systems Proceedings, 19 May. 2024, pp. 1-5, https://doi.org/10.1109/ISCAS58744.2024.10558315.