Post-LUT-Mapping Implementation of General Logic on Carry Chains Via a MIG-Based Circuit Representation

• Published in: International Conference on Field-programmable Logic and Applications pp. 334 - 340
• Main Authors: Kim, Jin Hee, Anderson, Jason
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2021
• Subjects: Arithmetic; Benchmark testing; CAD; carry chain; Delays; Field programmable gate arrays; FPGA; Logic functions; Optimization; Table lookup; technology mapping
• ISSN: 1946-1488
• DOI: 10.1109/FPL53798.2021.00065

Carry chains on FPGAs have traditionally been only used for fast binary arithmetic operations. In this paper, we propose using the carry chain to implement general logic as a means of reducing the critical path delay and raising performance. To achieve this, we use a Majority-Inverter Graph (MIG) to represent the application during technology mapping, since carry functionality directly maps to the majority logic function. This aligns the subject graph of technology mapping with the capabilities of the carry chain. We first map an application to LUTs, then determine a chain of critical LUTs containing paths of majority "gates" that we deem beneficial for mapping onto the carry chain. We place such paths onto the carry chains, with the remaining logic in LUTs. In an experimental study using a suite of benchmarks, we observe that the proposed approach yields a post-place-and-route critical path delay that is superior to using delay-optimized mapping, yet without the significant area penalty. With carry-chain optimizations, area-delay product is improved by 9% vs. baseline LUT mappings.