Galois Field Arithmetic Operations using Xilinx FPGAs in Cryptography

• Published in: 2021 IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS) pp. 1 - 6
• Main Authors: Balupala, Hari Krishna, Rahul, Kumar, Yachareni, Santosh
• Format: Conference Proceeding
• Language: English
• Published: IEEE 21.04.2021
• Subjects: Advanced Encryption Standard (AES); Affine-transformation; Conferences; Data Encryption Standard (DES); Encryption; Extended Euclidean Algorithm (EEA); Field Programmable Gate Array (FPGA); Galois field (GF); Galois fields; Greatest Common Divisor (GCD); Industries; Inverse Substitution; Logic gates; Mechatronics; Side-channel attacks; Substitution Box (S-box)
• DOI: 10.1109/IEMTRONICS52119.2021.9422551

Cryptography algorithms are standards for any security-based industry. Internationally widely accepted and used cryptography algorithms like AES, DES rely heavily on finite field arithmetic which needs to be performed efficiently, to meet execution speed and design constraints. This paper aims to provide a concise perspective on designing efficient architectures in finite field arithmetic. In this paper, we propose Galois field arithmetic using irreducible polynomial to generate the S-box for AES using 128, 192, and 256-bit Keys. Cryptographic algorithms are more prone to side-channel attacks, so we implemented this algorithm instead of using a lookup table-based approach. The proposed Galois Field implementation of arithmetic operations are unique which can be extended to any primitive polynomial of any word size GF(2 n ). A novel scheme is proposed for AES S-box, Inverse S-box, and validated using a Xilinx Virtex-7 FPGA.