Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm with Key Schedule and Sub Bytes Block Optimization - Gunasekaran, Mahendrakumar; Rahul, Kumar; Yachareni, Santosh (2021 IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS), 2021)
Keywords: add (add round key); AES (Advanced Encryption Standard); Encryption; FPGA (field programmable gate array); Hardware; LUT (Look up table); Mbps (megabit per second); mix (mix column); Registers; Schedules; shift (shift rows); sub (sub bytes); Table lookup; Throughput; Wireless communication