A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures - Igawa, Koki; Youhua Shi; Yanagisawa, Masao; Togawa, Nozomu (Proceedings / IEEE International SOC Conference, 2015)
Keywords: Algorithms; Architecture; Binding; Chips; Clocks; Conferences; Data transfer; Delays; hdr architecture; high-level synthesis; Integrated circuit interconnections; interconnection delay; Large scale integration; Multiplexing; process variation; Registers; scenario; Synthesis; System on chip