A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures

• Published in: Proceedings / IEEE International SOC Conference pp. 7 - 12
• Main Authors: Igawa, Koki, Youhua Shi, Yanagisawa, Masao, Togawa, Nozomu
• Format: Conference Proceeding Journal Article
• Language: English
• Published: IEEE 01.09.2015
• Subjects: Algorithms; Architecture; Binding; Chips; Clocks; Conferences; Data transfer; Delays; hdr architecture; high-level synthesis; Integrated circuit interconnections; interconnection delay; Large scale integration; Multiplexing; process variation; Registers; scenario; Synthesis; System on chip
• ISSN: 2164-1706
• DOI: 10.1109/SOCC.2015.7406898

In order to tackle a process-variation problem, we can define several scenarios, each of which corresponds to a particular LSI behavior, such as a typical-case scenario and a worst-case scenario. By designing a single LSI chip which realizes multiple scenarios simultaneously, we can have a process-variation-tolerant LSI chip. In this paper, we propose a process-variation-aware low-latency and multi-scenario high-level synthesis algorithm targeting new distributed-register architectures, called HDR architectures. We assume two scenarios, a typical-case scenario and a worst-case scenario, and realize them onto a single chip. We first schedule/bind each of the scenarios independently. After that, we commonize the scheduling/binding results for the typical-case and worst-case scenarios and thus generate a commonized area-minimized floorplan result. Experimental results show that our algorithm reduces the latency of the typical-case scenario by up to 50% without increasing the latency of the worst-case scenario, compared with several existing methods.