Improved write margin for 90nm SOI-7T-SRAM by look-ahead dynamic threshold voltage control

Instability of SRAM memory cells derived from aggressive technology scaling has recently been one of the most significant issues. Although a 7T-SRAM cell with an area-tolerable separated read port improves read margins even at sub-lV, it unfortunately results in degradation of write margins. Then, w...

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Bibliographic Details
Published in2007 50th Midwest Symposium on Circuits and Systems pp. 578 - 581
Main Authors Iijima, M., Seto, K., Numa, M., Tada, A., Ipposhi, T.
Format Conference Proceeding Journal Article
LanguageEnglish
Japanese
Published IEEE 01.08.2007
Subjects
Acceleration
Boosting
Degradation
Driver circuits
MOS devices
MOSFETs
Random access memory
Threshold voltage
Variable structure systems
Voltage control
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ISBN1424411750
9781424411757
ISSN1548-3746
DOI10.1109/MWSCAS.2007.4488649

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Summary:Instability of SRAM memory cells derived from aggressive technology scaling has recently been one of the most significant issues. Although a 7T-SRAM cell with an area-tolerable separated read port improves read margins even at sub-lV, it unfortunately results in degradation of write margins. Then, we address a new memory cell adopting a look-ahead body-bias which dynamically controls the threshold voltage in order to assist the write operation. Simulation results have shown improvement in both the write margins and access time.
ISBN:1424411750
9781424411757
ISSN:1548-3746
DOI:10.1109/MWSCAS.2007.4488649