MOTPE/D: Hardware and Algorithm Co-design for Reconfigurable Neuromorphic Processor

• Published in: Proceedings - IEEE International Conference on Computer Design pp. 521 - 524
• Main Authors: Li, Yuan, Chen, Renzhi, Yang, Zhijie, Xiao, Xun, Zhao, Jingyue, Zhu, Zhenhua, Dai, Huadong, Tang, Yuhua, Xu, Weixia, Luo, Li, Wang, Lei
• Format: Conference Proceeding
• Language: English
• Published: IEEE 18.11.2024
• Subjects: Analytical models; Hardware; hardware/algorithm co-design; multi-objective optimization; Network architecture; neuromorphic processor; Neuromorphics; Optimization; Power demand; spiking neural network; Spiking neural networks
• ISSN: 2576-6996
• DOI: 10.1109/ICCD63220.2024.00086

Recent advances in hardware/algorithm co-design for spiking neural networks have demonstrated its potential for jointly optimizing algorithmic performance while minimizing hardware overhead. However, the gigantic mixed-variable hard-ware/algorithm co-design space and time-consuming hardware verification still pose an intractable challenge for solutions exploration. To tackle these problems, 1) we propose a generic three-phase hardware/algorithm co-design framework. In this framework, 2) we target a reconfigurable neuromorphic processor, and parameterize the hardware and network architecture in a unified design space. 3) We propose a generic analytical model to estimate the parameter size and power consumption, which can support fast candidate evaluation during the exploration. 4) We extend vanilla TPE (a single-objective optimization algorithm) to MOTPE/D, a generic Multi-objective optimization (MOO) algorithm, by introducing a decomposition strategy.