APA (7th ed.) Citation

Gu, T., Wang, J., Bi, Z., Yan, C., Yang, F., Qin, Y., . . . Zeng, X. (2024, March 25). tSS-BO: Scalable Bayesian Optimization for Analog Circuit Sizing via Truncated Subspace Sampling. Proceedings - Design, Automation, and Test in Europe Conference and Exhibition, 1-6. https://doi.org/10.23919/DATE58400.2024.10546770

Chicago Style (17th ed.) Citation

Gu, Tianchen, Jiaqi Wang, Zhaori Bi, Changhao Yan, Fan Yang, Yajie Qin, Tao Cui, and Xuan Zeng. "TSS-BO: Scalable Bayesian Optimization for Analog Circuit Sizing via Truncated Subspace Sampling." Proceedings - Design, Automation, and Test in Europe Conference and Exhibition 25 Mar. 2024: 1-6. https://doi.org/10.23919/DATE58400.2024.10546770.

MLA (9th ed.) Citation

Gu, Tianchen, et al. "TSS-BO: Scalable Bayesian Optimization for Analog Circuit Sizing via Truncated Subspace Sampling." Proceedings - Design, Automation, and Test in Europe Conference and Exhibition, 25 Mar. 2024, pp. 1-6, https://doi.org/10.23919/DATE58400.2024.10546770.