PatRouter: An Optimal-Pattern-Oriented Routability-Driven Routing Algorithm for FPGA

• Published in: 2024 2nd International Symposium of Electronics Design Automation (ISEDA) pp. 433 - 438
• Main Authors: Wu, Chen, Li, Xuhui, Wang, Qiang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 10.05.2024
• Subjects: Benchmark testing; Design automation; Field programmable gate arrays; FPGA routing; Generators; Optimal-pattern; Routability-driven; Routing; Runtime; Wire
• DOI: 10.1109/ISEDA62518.2024.10617779

Quality of routing results is one of the most significant aspects for modern FPGA design. Although various attempts have been made on improving routability and runtime, the existing approaches pay little attention on the nature of PathFinder-based routers to optimize the quality of routing results. In this paper, we propose PatRouter, an optimal-pattern-oriented routability-driven algorithm to improve the quality of routing. A pattern generator is first developed to build optimal patterns, which is defined as routing paths with the minimal number of wire segments to represent the routing resources in device. On this basis, we propose a pattern-oriented min-segment (PoM) connection router, which intensively route connections with optimal patterns. In this way, PoM searches for routing paths under pruned routing resources, thus, also reducing runtime. Meanwhile PoM will gradually increase the number of wire segments for congested connections to maintain routability. To further improve routability, we design a pattern-oriented A * (PoA) connection router to address the most congested connections by searching the whole routing resources. Experiments on our self-defined architecture and benchmarks show that PatRouter optimizes the quality of routing results while maintaining routability. To be specific, with PatRouter, 46.9% of the total connections are routed with minimal number of wire segments on average. Meanwhile, 22.2% of the total connections need sub-optimal patterns within 2 wire segments from optimal. Comparison with the latest approaches on Titan benchmark also shows 1.2× reduction in wirelength.