Demystifying Datapath Accelerator Enhanced Off-path SmartNIC

• Published in: Proceedings - International Conference on Network Protocols pp. 1 - 12
• Main Authors: Chen, Xuzheng, Zhang, Jie, Fu, Ting, Shen, Yifan, Ma, Shu, Qian, Kun, Zhu, Lingjun, Shi, Chao, Zhang, Yin, Liu, Ming, Wang, Zeke
• Format: Conference Proceeding
• Language: English
• Published: IEEE 28.10.2024
• Subjects: Guidelines; Hands; Hardware; Logic; Multicore processing; Process control; Program processors; Protocols; Telecommunication traffic; Throughput
• ISSN: 2643-3303
• DOI: 10.1109/ICNP61940.2024.10858560

Network speeds grow quickly in the modern cloud, so SmartNICs are introduced to offload network processing tasks, even application logic. However, typical multicore SmartNICs such as BlueFiled-2 are only capable of processing control-plane tasks with their embedded processors that have limited memory bandwidth and computing power. On the other hand, cloud applications evolve rapidly, such that a limited number of fixed hardware engines in a SmartNIC cannot satisfy the requirements of cloud applications. Therefore, SmartNIC programmers call for a programmable datapath accelerator (DPA) to process network traffic at line rate. However, no existing work has unveiled the performance characteristics of the existing DPA. To this end, we present the first architectural characterization of the latest DPA-enhanced BlueFiled-3 (BF3) SmartNIC. Our evaluation results indicate that BF3's DPA is significantly wimpier than the off-path Arm processor and the host CPU. However, we still identify that DPA has three unique architectural characteristics that unleash the performance potential of DPA. Specifically, we demonstrate how to take advantage of DPA's three architectural characteristics regarding computing, networking, and memory subsystems. Then we propose three important guidelines for programmers to fully unleash the potential of DPA. To demonstrate the effectiveness of our approach, we conduct detailed case studies regarding each guideline. Our case study on key-value aggregation achieves up to 4.3 \times higher throughput by using our guidelines to optimize memory combinations.