High-level synthesis algorithms with floorplaning for distributed/shared-register architectures - Ohchi, A.; Togawa, N.; Yanagisawa, M.; Ohtsuki, T. (2008 International Symposiium on VLSI Design, Automation and Test, 2008)
Keywords: Clocks; Computer architecture; Computer science; Delay; Hardware; High level synthesis; Integrated circuit interconnections; Processor scheduling; Registers; Wire