Formalized Hardware Design Process by an Example of Building Energy Efficient Sensor Network for Computational Algorithm

• Published in: 2007 9th International Conference - The Experience of Designing and Applications of CAD Systems in Microelectronics pp. 207 - 210
• Main Author: Vizgalov, E.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.02.2007
• Subjects: Algorithm design and analysis; architecture; Buildings; Computer architecture; Computer languages; Computer networks; Energy efficiency; energy-efficient; formal system; Hardware; hardware design; Pipelines; Process design; sensor network; Software algorithms
• ISBN: 9665335870
• DOI: 10.1109/CADSM.2007.4297527

The technology of hardware algorithm design process is considered. It is shown the possibility of creating the formal system which allows generating different hardware solutions based upon the same basic algorithm. It is achieved by having a number of intermediate descriptions for the basic algorithm which are gradually refine it and finally transform it to the hardware. E.g. first algorithm is described abstractly and at the next step it is described with taking into account computational resources as registers, memory, processors. Different hardware implementations are results of formal algorithm transformations from one representation to another. It is shown that common hardware architectures as state machines, pipelines and synchronization elements can be described as templates and the basic algorithm once described can be easily ported to different architectures. The idea is elaborated by an example of simple computational algorithm and its different implementations including the form of the sensor network. The formal process is shown and analysis of different implementations by energy efficiency criteria is considered.